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1 zarlink semiconductor inc. zarlink, zl and the zarlink semiconductor logo are trademarks of zarlink semiconductor inc. copyright 2003-2006, zarlink semiconductor inc. all rights reserved. features ? zl50211 has eight echo voice processors in a single bga package. this single device provides 256 channels of 64 msec echo cancellation or 128 channels at 128 msec echo cancellation ? each echo voice processor has the capability of cancelling echo over 32 channels ? each echo voice processor (evp) shares the address bus and data bus with each other ? fully compliant to itu-t g.165, g.168 (2000) and (2002) specifications ? passed all at&t voice quality tests for carrier grade echo canceller ? the zl50211 provides more than 58% board space savings when compared with the eight echo voice processors packaged devices ? each evp has a patented advanced non-linear processor with high quality subjective performance ? each evp has protection against narrow band signal divergence and instability in high echo environments ? each evp can be programmed independently in any mode e.g., back-to-back or extended delay to provide capability of cancelling different echo tails ? each evp has 0 to -12 db level adjusters at all signal ports (rin, sin, sout and rout) ? each evp has the same jtag identification code applications ? voice over ip network gateways ? voice over atm, frame relay ? t1/e1/j1 multichannel echo cancellation ? wireless base stations ? echo canceller pools ? dcme, satellite and multiplexer system january 2006 ordering information zl50211gbc 535 ball bga trays zl50211gbg2 535 ball bga** trays **pb free tin/silver/copper -40 c to +85 c zl50211 256 channel voice echo canceller data sheet figure 1 - zl50211 device overview evp1 rin1...rin8 sin1....sin8 cs 1..cs 8 d0....d7 a0..a12 reset 1..reset 8 r/w mlck c4i fo i ode ds fsel rout1..rout8 sout1..sout8 irq 1.. irq 8 dta 1.. dta 8 evp4 evp6 evp7 evp8 evp5 evp3 evp2 zl50211gb
zl50211 data sheet 2 zarlink semiconductor inc. description the zl50211 voice echo canceller implements a cost effective solution for telephony voice-band echo cancellation conforming to itu-t g.168 requirements. the zl50211 arch itecture contains 128 groups of two echo cancellers (eca and ecb) which can be configured to provide tw o channels of 64 milliseconds or one channel of 128 milliseconds echo canc ellation. this provides 256 channels of 64 milliseconds to 12 8 channels of 128 milliseconds echo cancellation or any combination of the two configurations. the zl502 11 supports itu-t g.165 and g.164 tone disable requirements. figure 2 - single echo voic e processor (evp) overview reset rout ic0 sout ds cs r/w a12-a0 dta d7-d0 echo canceller pool v ss v dd1 (3.3v) tdi tdo tck trst tms rin irq c4i f0i mclk ode sin fsel test port microprocessor interface timing unit serial to parallel parallel to serial pll group 0 eca/ecb group 4 eca/ecb group 8 eca/ecb group 12 eca/ecb group 1 eca/ecb group 5 eca/ecb group 9 eca/ecb group 13 eca/ecb group 2 eca/ecb group 6 eca/ecb group 10 eca/ecb group 14 eca/ecb group 3 eca/ecb group 7 eca/ecb group 11 eca/ecb group 15 eca/ecb note: refer to figure 4 for evp block diagram v dd2 (1.8v)
zl50211 data sheet 3 zarlink semiconductor inc. features of echo voice processor (evp) ? each evp can cancel echo tails of 64 ms (32 channels) to 128 ms (16 channels) with the ability to mix channels at 128 ms or 64 ms in any combination ? independent power down mode for each group of 2 channels for power management ? fully compliant to itu-t g.165, g.168 (2000) and (2002) specifications ? passed all at&t voice quality tests for carrier grade echo canceller ? compatible to st-bus and gci interface at 2 mb/s serial pcm ? pcm coding, /a-law itu-t g.711 or sign magnitude ? per channel fax/modem g.164 2100 hz or g.165 2100 hz phase reversal tone disable ? per channel echo canceller parameters control ? transparent data transfer and mute ? fast reconvergence on echo path changes ? fully programmable convergence speeds ? patented advanced non-linear processor wi th high quality subjective performance ? protection against narrow band signal divergence and instability in high echo environments ? 0 db to -12 db level adjusters (3 db steps) at all signal ports ? offset nulling of all pcm channels ? 10 mhz or 20 mhz master clock operation ? 3.3 v pads and 1.8 v logic core operation with 5-volt tolerant inputs ? ieee-1149.1 (jtag) test access port
zl50211 data sheet 4 zarlink semiconductor inc. figure 3 - 535 ball bga ball grid array 1 b c d e f g h j k l m n a p r t u v w y 12 345 67 8910111213 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 aa aj ak ag ae ah ad ac ab af b c d e f g h j k l m n a p r t u v w y aa aj ak ag ae ah ad ac ab af 1 2 3 4 5 6 7 8 910111213 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 zl50211gb bga ball grid array
zl50211 data sheet 5 zarlink semiconductor inc. pin description signal name signal type bga ball # signal description v dd1 = 3.3v (v dd_io ) power ac5,ac26,ac27,ad26,ad5,ae5,af12,af13,af1 4,af17,af18,af19,af24,af6,af7,af8,ag24,ah 24,e13,e14,e17,e18,e19,e23,e24,e25,e6,e7,e8, f5,g26,g27,g5,h26,h5,m26,m5,n26,n5,p26,p27 , p4,p5,u26,u27,u4,u5,v26,v5,w26,w5 positive power supply. nominally 3.3 volt (i/o voltage). v dd2 = 1.8v (v dd_core ) power aa26,aa28,aa3,aa5,ab26,ab28,ab3,ab5,af11, af20,ag10,ag21,ag22,ah10,ah11,ah22,aj15, aj16,aj9,ak9,c10,c11,c22,c23,c9,d10,d23,d9, e11,e20,e21,e22,j26,j27, j4,j5,k26,k27,k3,k5, l26,l27,l3,l5,y26, y27,y3,y5 positive power supply. nominally 1.8 volt (core voltage). vss power a29,a30,af5,ag15,ag16,ag26,ag27,ag4,ah15 , ah16,ah21,ah28,ah3,aj2,aj21,aj29,ak1,ak30, b1,b15,b16,b2,b29,c15,c16,c28,c3,d15,d16, d27,d4,e26,e5,n13,n14,n15,n16,n17,n18,p13, p14,p15,p16,p17,p18,r1 3,r14,r15,r16,r17, r18,r2,r27,r28,r29,r3,r 4,t13,t14,t15,t16, t17,t18,t2,t27,t28,t29, t3,t4,u13,u14,u15, u16,u17,u18,v13,v14,v15,v16, v17,v18 ground test pins te1, te2, te3, te4, te5, te6, te7, te8 test mode pins m4,ak26,m3,aj4,ak4,ak25,k30,n28 internal connection. connected to vss for normal operation. output test pins te s t pins d8,p28,c12,ak10,ah12,ad29,h28,j29,ac28, d12,p29,e9,aj11,ak11,ad30,g28,h29,ab27,a3, p2,a2,y1,aa1,aj17,c20,b21,ak17,b3,p1,d3, aa2,ab1,ak18,b22,d21,aj18,c2,r1,e3,ab2, ab4,ah18,d19,a22,ak19,d2,t1,e4,ac1,ac2, ag18,a21,b20,aj19,c1,u1,f4,ac4,ad1,ak20, c19,a20,ah19,f3,u2,e2,ac3,ad2,ak21,b19, a19,ag19,e10,p30,b12, aj12,ag13,ac29,j30, g29,ac30,a11,n30,d11,ah13,ak12,ab29,h30, g30,ab30,a10,n27,b11,aj13,ag14,aa27,f29, f30,aa29,a9,a14,b10,ag11,ag12,y28,e29,e28, aa30,a8,a13,b9,aj10,af10,y29,d29,e30,y30, c8,b14,b8,ag9,ah9,w28,d26,d28,w29,c4, e12,c5,aa4,y4,r30,a23,b23, t30,b4,p3,a4,y2,w1,ag17,d20,c21,ah17 no connection. these pins must be left open for normal operation.
zl50211 data sheet 6 zarlink semiconductor inc. input test pins sc_en, sc_fclk, sc_in, sc_m_mclk, sc_reset, sc_set, sc_t_mclk, a27,d5,a25,a26,a24,b24,a28 internal connection. connected to vss for normal operation. thalt and tstep halt step c14, d14 internal connection. connected to vss for normal operation. signal name signal type bga ball # signal description user signal pins d0, d1, d2, d3, d4, d5, d6, d7 user signals ak7,aj8,ak8, aj27,ak29,aj28, ah27, aj30 data bus d0 to d7 (bidirectional). these pins form the 8-bit bidirectional data bus of the microprocessor port. they are connected to all the evp?s. a0,a1,a2,a3,a4,a5, a6,a7, a8, a9, a10,a11,a12 user signals ag28,ah29, ah30,ag29,af28, ag30,ae28,af29, ae29,af30,ad27, ae30,ad28 address a0 to a12 (input). these inputs provide the a12 - a0 address lines to the internal registers. they are connected to all the evp?s. cs 1,cs 2,cs 3, cs 4, cs 5, cs 6, cs 7, cs 8 user signals r5,l28,t5,af15, af16,e16,t26, r26 chip select (input). these active low inputs are used enable the microprocessor interface of each evp. reset 1 reset 2, reset 3, reset 4, reset 5, reset 6, reset 7, reset 8 user signals m2,ah23,m1,ah5, aj5,aj23,n29,m30 evp reset (schmitt trigger input). an active low resets the device and puts the voice processor into a low-power stand-by mode. when the reset pin is returned to logic high and a clock is applied to the mclk pin, the evp will automatically execute initialization routines, which preset all the control and status registers to their default power-up values. each reset pin controls a single processor. a user can connect all of them together if required. rin1,rin2,rin3, rin4,rin5,rin6, rin7,rin8 user signals c6,v27,b5,ag5, ah6,u28,b27,b28 receive pcm signal inputs (input). port 1 tdm data input streams. each rin pin receives serial tdm data streams at 2.048 mb/s wi th 32 channels per stream. sin1,sin2,sin3,sin4, sin5,sin6,sin7,sin8 user signals c7,u30,b6,ag7, ag6,u29,b30,c27 send pcm signal inputs (input). port 2 tdm data input streams. each sin pi n receives serial tdm data streams at 2.048 mb/s wi th 32 channels per stream. pin description (continued) signal name signal type bga ball # signal description
zl50211 data sheet 7 zarlink semiconductor inc. rout1,rout2,rout3, rout4,rout5,rout6, rout7,rout8, user signals a5,v30,a6,ah7, ag8,v28,c26,c30 receive pcm signal outputs (output). port 2 tdm data output streams. each rout pin outputs serial tdm data streams at 2.048 mb/s with 32 channels per stream. sout1,sout2,sout3, sout4,sout5,sout6, sout7,sout8 user signals b7,w27,a7,ah8, af9,w30,c29,d30 send pcm signal outputs (output). port 1 tdm data output streams. each s out pin outputs serial tdm data streams at 2.048 mb/s with 32 channels per stream. ds user signal k29 data strobe (input). this active low input works in conjunction with cs to enable the read and write operations. this signal is connected to all processors. r/w user signal m29 read/write (input). this input controls the direction of the data bus lines (d7-d0) during a microprocessor access. this signal is connected to all processors. dta 1, dta 2, dta 3, dta 4, dta 5, dta 6, dta 7, dta 8 user signals n2,ak28,n1,ak6, aj7,ak27,m28, m27 data transfer acknowledgment (open drain output). these active low outputs indicate that a data bus transfer is completed. a pull-up resistor (1 k typical) is requir ed at these outputs. ode user signal v29 output drive enable (input). this input pin is logically and?d with the ode bit-6 of the main control register. when both ode bit and ode input pin are high, the rout and sout st-bus outputs are enabled. when the ode bit is low or the ode input pin is low, the rout and sout st-bus outputs are high impedance. this signal is connected to all processors. f0i user signal b26 frame pulse (input). this input accepts and automatically identifies fr ame synchronization signals formatted according to st-bus or gci interface specifications.this signal is connected to all processors. c4i user signal b25 serial clock (input). 4.096 mhz serial clock for shifting data in/out on the serial streams (rin, sin, rout, sout).this signal is connected to all processors. fsel user signal a15 frequency select (input). this input selects the mas- ter clock frequency operation. when fsel pin is low, nominal 20 mhz master clock input must be applied. when fsel pin is high, no minal 10 mhz master clock input must be applied.this signal is connected to all processors. mclk user signal a16 master clock (input). nominal 10 mhz or 20 mhz master clock input. may be connected to an asynchronous (relative to frame signal) clock source.this signal is connected to all processors. signal name signal type bga ball # signal description
zl50211 data sheet 8 zarlink semiconductor inc. irq 1, irq 2, irq 3, irq 4, irq 5, irq 6, irq 7, irq 8 user signals n4,aj26,n3,ak5, aj6,ag23,l30,l29 interrupt request (open drain output). these outputs go low when an interrupt occurs in any channel. each irq returns high when all the interrupts have been read from the interrupt fifo register of respective evp. a pull-up re sistor (1 k typical) is required at these outputs. extra device pins - w3,e15,v4,ak16, ak15,ak14,d13, c13,v3,a12,b13, ak13,ah14,u3,v2, aj14 no connection. the ball pins must be left open for normal operation. jtag signal pins tms jtag signal k2 test mode select (3.3 v input). jtag signal that controls the state transitions of the tap controller. this pin is pulled high by an internal pull-up when not driven. this signal is connected to all processors. tck jtag signal d6 test clock (3.3 v input). provides the clock to the jtag test logic.this signal is connected to all processors. trst jtag signal d7 test reset (3.3 v input). asynchronously initializes the jtag tap controller by putting it in the test-logic- reset state. this pin should be pulsed low on power- up or held low, to ensure that all the evp?s are in the normal functional mode. this pin is pulled by an internal pull-down when not driven. this signal is connected to all evp?s. tdi1,tdi2,tdi3,tdi4, tdi5,tdi6,tdi7,tdi8 jtag signals k1,ak23,l2,ak2, aj3,ah20,f27,h27 test serial data in (3.3 v input). jtag serial test instructions and data are shifted in on these pins. these pins are pulled high by an internal pull-up when not driven. tdo1,tdo2,tdo3, tdo4,tdo5,tdo6 tdo7,tdo8 jtag signals l1,aj22,l4,ah4, ak3,ak24,j28,k28 test serial data out (output). jtag serial data is outputted on these pins on the falling edge of tck. these pins are held in high impedance state when jtag scan is not enabled. pll signal pins pllv dd2 = 1.8v pll power h3,v1,h4,ae3, ag2,ae26,d22, c24, ae27 pll power supply. must be connected to pllv dd2 = 1.8v. pllv ss1 pllv ss2 pll power j3,w2,h2,af4, af3,af27,d24, c25,af26,h1,w4, j2, ah1,ag3,af22, d25,e27,af21 pll ground. must be connected to vss. signal name signal type bga ball # signal description
zl50211 data sheet 9 zarlink semiconductor inc. the following description applies to a single evp (echo vo ice processor). note that the zl50211 contains eight evp?s. 1.0 single echo voice processor (evp) description each single echo voice processor (evp) contains 32 echo cancel lers divided into 16 gr oups. each group has two echo cancellers, echo canceller a (eca) and echo cance ller b (ecb). each group can be configured in normal, extended delay or back-to-back configurations. in normal configuration , a group of echo cancellers provides two channels of 64 ms echo cancellation, which run independently on different channels. in extended delay configuration, a group of echo cancellers achieves 128 ms of echo cancellation by cascading the two echo cancellers (a & b). in back-to-back configuration, the two echo cancellers from the same group are positioned to cancel echo coming from both directions in a single channel, providing full-duplex 64 ms echo cancellation. each echo voice processor contains the following main elements (see figure 4). ? adaptive filter for estimating the echo channel ? subtractor for cancelling the echo ? double-talk detector for disabling the filt er adaptation during periods of double-talk ? path change detector for fast reconvergence on major echo path changes ? instability detector to combat instability in very low erl environments ? patented advanced non-linear processor for suppression of residual echo, with comfort noise injection ? disable tone detectors for detecting valid disable tones at send and receive path inputs ? narrow-band detector for preventing adaptive filter divergence from narrow-band signals ? offset null filters for removing the dc component in pcm channels ? 0 to -12 db level adjusters at all signal ports ? parallel controller interface compatib le with motorola microcontrollers ? pcm encoder/decoder compatible with /a-law itu-t g.711 or sign-magnitude coding t1m1, t1m2, t1m3, t1m4, t1m5, t1m6, t1m7, t1m8 pll test signals d1,ah26,e1,ae1, ad4,ak22,d18, c18 internal connection. connected to vss for normal operation. t2m1, t2m2, t2m3, t2m4, t2m5, t2m6, t2m7, t2m8 pll test signals f2,ag25,g3,af1, ad3,af25,b18,a18 internal connection. connected to vss for normal operation. sg1, sg2, sg3, sg4, sg5, sg6, sg7, sg8 pll test signals g4,aj25,f1,ae2, ag1, ah25,b17,c17 internal connection. connected to vss for normal operation. dt1, dt2, dt3, dt4, dt5, dt6, dt7, dt8 pll test signals g2,af23,g1,af2, ae4,aj24,d17, a17 no connection. these pins must be left open for normal operation. at1, at2, at3, at4, at5, at6, at7, at8 pll test signals k4,aj20,j1, ah2,aj1,ag20, f28,f26 no connection. these pins must be left open for normal operation. signal name signal type bga ball # signal description
zl50211 data sheet 10 zarlink semiconductor inc. ? each echo canceller in the evp has four functional states: mute, bypass, disable adaptation and enable adaptation. these are explained in the section entitled echo canceller functional states. figure 4 - functional block diagram of an echo canceller 1.1 adaptive filter the adaptive filter adapts to the echo path and generates an es timate of the echo signal. this echo estimate is then subtracted from sin. for each group of echo cancellers, the adaptive filter is a 1024 tap fir adaptive filter which is divided into two sections. each section contains 512 taps providing 64 ms of echo estimation. in normal configuration , the first section is dedicated to channel a and the second section to channel b. in extended delay configuration , both sections are cascaded to provide 128 ms of echo estimation in channel a. in back-to-back configuration , the first section is used in the receive directi on and the second section is used in the transmit direction for the same channel. 1.2 double-talk detector double-talk is defined as those period s of time when signal energy is pres ent in both directions simultaneously. when this happens, it is necessary to disable the filt er adaptation to prevent dive rgence of the adaptive filter coefficients. note that when double-ta lk is detected, the adaptation proces s is halted but the echo canceller continues to cancel echo using the previous converged echo profile. a double-talk condition exists whenever the relative signal levels of rin (lrin) and sin (lsin) meet the following condition: lsin > lrin + 20log 10 (dtdt) where dtdt is the double-talk dete ction threshold. lsin and lrin ar e signal levels expressed in dbm0. a different method is used when it is uncertain whethe r sin consists of a low level double-talk signal or an echo return. during these periods, the adaptation process is slowed down but it is not halted. the slow convergence speed is set using the slow sub-register in control regi ster 4. during slow converg ence, the adaptation speed is reduced by a factor of 2 slow relative to normal convergence for non-ze ro values of slow. if slow equals zero, adaptation is halted completely. non-linear processor offset null linear/ /a-law microprocessor interface double - talk detector control narrow-band detector /a-law/ linear offset null echo canceller (n), where 0 < n < 31 sout rin sin rout - programmable bypass (channel n) (channel n) (channel n) (channel n) st-bus st-bus port2 port1 muter mutes 0 to -12db level adjust linear/ /a-law 0 to -12db level adjust 0 to -12db level adjust /a-law/ linear 0 to -12db level adjust adaptive filter disable tone detector disable tone detector detector path change instability detector
zl50211 data sheet 11 zarlink semiconductor inc. in the g.168 standard, the echo return loss is expected to be at least 6 db. this implies that the double-talk detector threshold (dtdt) should be set to 0.5 (-6 db). however, in order to achieve additional guardband, the dtdt is set internally to 0.5625 (-5 db). in some applications the return loss can be higher or lower than 6 db. the evp allows the user to change the detection threshold to suit each application?s need. this threshold can be set by writing the desired threshold value into the dtdt register. the dtdt register is 16 bits wide. th e register value in hexadecimal can be calculated with the following equation: dtdt (hex) = hex(dtdt (dec) * 32768) where 0 < dtdt (dec) < 1 example:for dtdt = 0.5625 (-5 db), the hexadecimal value becomes hex( 0.5625 * 32768 ) = 4800 hex 1.3 path change detector integrated into the evp is a path chan ge detector. this permits fast reconvergence when a major change occurs in the echo channel. subtle changes in the echo channel are also tracked automatically once convergence is achieved, but at a much slower speed. the path change detector is activated by setting the path det bit in control register 3 to ?1?. an optional path clearing feature can be enabled by setting the pathclr bit in control register 3 to ?1?. with path clearing turned on, the existing echo channel estimate will also be cleared (i.e ., the adaptive filter will be filled with zeroes) upon detection of a major path change. 1.4 non-linear processor (nlp) after echo cancellation, there is always a small amount of residual echo which may still be audible. the evp uses zarlink?s patented advanced nlp to remove residual echo signals whic h have a level lower than the adaptive suppression threshold (tsup in g.168). this threshold depends upon the level of the rin (lrin) reference signal as well as the programmed value of the non-linear processor threshol d register (nlpthr). tsup can be calculated by the following equation: tsup = lrin + 20log 10 (nlpthr) where nlpthr is the non-linear processor threshold register value and lrin is the relative power level expressed in dbm0. the nlpthr register is 16 bits wide. the regi ster value in hexadecimal can be calculated with the following equation: nlpthr (hex) = hex(nlpthr (dec) * 32768) where 0 < nlpthr (dec) < 1 when the level of residual error signal falls below tsup, the nlp is activated further attenuating the residual signal by an additional 30 db. to prevent a perceived decrease in background noise due to the activation of the nlp, a spectrally-shaped comfort noise , equivalent in power level to the backgr ound noise, is injected. this keeps the perceived noise level constant. cons equently, the user does not hear the ac tivation and de-activation of the nlp. the nlp processor can be disabled by setting the nlpdis bit to ?1? in control register 2. the comfort noise injector can be disabled by setting the in jdis bit to ?1? in control r egister 1. it should be noted that the nlpthr is valid and the comfort noise in jection is active only when the nlp is enabled.
zl50211 data sheet 12 zarlink semiconductor inc. the patented advanced nlp provides a number of new and improved features over the original nlp found in previous generation devices. the differences between t he advanced nlp and the original nlp are summarized in table 1. the nlpsel bit in control register 3 se lects which nlp is used. a ?1? will sele ct the advanced nlp, ?0? selects the original nlp. the advanced nlp uses a new noise ramping scheme to quickly and more accurately estimate the background noise level. the noise ramping method of the original nlp can also be used. the injctrl bit in control register 3 selects the ramping scheme. the nlinc sub-register in noise control is used to se t the ramping speed. when injctrl = 1 (such as with the advanced nlp), a lower value will give faster ramping. when injctrl = 0 (suc h as with the original nlp), a higher value will give faster ramping. nlinc is a 4-bit value, so only values from 0 to f(hex) are valid. the noise scaling register can be used to adjust the rela tive volume of the comfort noise. lowering this value will scale the injected noise level down, conversely, raising the value will scale the comfort noise up. due to differences in the noise estimator operation, the advanced nlp r equires a different scaling valu e than the original nlp. important note : nlinc and the noise scaling register have been pre-programmed with g.168 compliant values. changing these values may result in undesirable comfort noise performance! the advanced nlp also contains safeguards to prevent double-talk and uncancelled echo from being mistaken for background noise. these features were not present in t he original nlp. they can be disabled by setting the nlrun1 and nlrun2 bits in control register 3 to ?0?. 1.5 disable tone detector the g.165 recommendation defines the disable tone as having the following characteristics: 2100 hz ( 21 hz) sine wave, a power level between -6 to -31 dbm0, and a phase reversal of 180 degrees ( 25 degrees) every 450 ms (25 ms). if the disable tone is present for a mini mum of one second with at least one phase reversal, the tone detector will trigger. the g.164 recommendation defines t he disable tone as a 2100 hz (+ 21 hz) sine wave with a power level between 0 to -31 dbm0. if the disable tone is present for a mini mum of 400 ms, with or without phase reversal, the tone detector will trigger. feature register or bit(s) advanced nlp default value original nlp default value nlp selection nlpsel (contro l register 3) 1 0 (feature not supported) reject uncancelled echo as noise nlr un1 (control regist er 3) 1 0 (feature not supported) reject double-talk as noise nlrun2 (control register 3) 1 0 (feature not supported) noise level estimator ramping scheme inj ctrl (control register 3) 1 0 (feature not supported) noise level ramping rate nlinc (noise control) 5(hex) c(hex) noise level scaling noise scaling 16(hex) 74(hex) table 1 - comparison of nlp types
zl50211 data sheet 13 zarlink semiconductor inc. each evp has two tone detectors per channels (for a total of 64) in order to monitor the occurrence of a valid disable tone on both rin and sin. upon detection of a disabl e tone, td bit of the status register will indicate logic high and an interrupt is generated (i.e., irq pin low). refer to figure 5 and to the interrupts section. figure 5 - disable tone detection once a tone detector has been triggered, there is no long er a need for a valid disable tone (g.164 or g.165) to maintain tone detector status (i.e., td bit high). the tone detector status will only rel ease (i.e. td bit low) if the signals rin and sin fall below -30 dbm0, in the frequency range of 390 hz to 700 hz, and below -34 dbm0, in the frequency range of 700 hz to 3400 hz, for at least 400 ms. whenever a tone detector releases, an interrupt is generated (i.e., irq pin low). the selection between g.165 and g.164 tone disable is cont rolled by the phdis bit in control register 2 on a per channel basis. when the phdis bit is set to ?1 ?, g.164 tone disable requirements are selected. in response to a valid disable tone, the echo canceller must be switched from the enable adaptation state to the bypass state. this can be done in two ways, automatica lly or externally. in automa tic mode, the tone detectors internally control the switching betw een enable adaptation and bypass states . the automatic mode is activated by setting the autotd bit in control register 2 to high. in external mode, an exte rnal controller is needed to service the interrupts and poll the td bits in the status registers. following the detection of a di sable tone (td bit high) on a given channel, the external controller must switch the echo canceller from enable adaptation to bypass state. 1.6 instability detector in systems with very low echo channel return loss (erl ), there may be enough feedback in the loop to cause stability problems in the adaptive filter . this instability can result in variab le pitched ringing or oscillation. should this ringing occur, the instab ility detector will activate and suppress the oscillations. the instability detector is activated by settin g the ringclr bit in control register 3 to ?1?. 1.7 narrow band signal detect or (nbsd) single or dual frequency tones (i.e. dtmf tones) present in the receive input (rin) of the echo canceller for a prolonged period of time may cause t he adaptive filter to diverge. the na rrow band signal detector (nbsd) is designed to prevent this by detecting single or dual to nes of arbitrary frequency, phase, and amplitude. when narrow band signals are detected, adaptation is halted but the echo canc eller continues to cancel echo. the nbsd will be active regardless of the evp functional state. however th e nbsd can be disabled by setting the nbdis bit to ?1? in control register 2. td bit rin sin echo canceller a tone detector tone detector status reg eca td bit rin sin echo canceller b tone detector tone detector status reg ecb
zl50211 data sheet 14 zarlink semiconductor inc. 1.8 offset null filter adaptive filters in general do not operate properly wh en a dc offset is present at any input. to remove the dc component, each evp incorporates offset null filters in both rin and sin inputs. the offset null filters can be disabled by setti ng the hpfdis bit to ?1? in control register 2. 1.9 adjustable level pads each evp provides adjustable level pads at rin, rout, sin and sout. this setup allows signal strength to be adjusted both inside and outside the echo path. each sig nal level may be independently scaled with anywhere from 0 to -12 db level, in 3 db steps. level values are set using the gains register. caution: gain adjustment can help interface the zl50211 to a particular system in order to provide optimum echo cancellation, but it can also degrade performance if not do ne carefully. excessive loss may cause low signal levels and slow convergence. exercise great care when adjusting these values. the -12 db pad bit in control register 1 is still supported as a legacy feature. setting this bit will provide 12 db of attenuation at rin, and override the values in the gains register. 1.10 itu-t g.168 compliance the zl50211 has been certified g.168 (1997), (2000) and (2 002) compliant in all 64 ms cancellation modes (i.e. normal and back-to-back configur ations) by in-house testing with the dspg ect-1 echo canceller tester. the zl50211 has also been tested for g.168 compliance and all voice quality tests at at&t labs. the zl50211 was classified as ?carrier grade? echo canceller. 2.0 evp configuration the evp architecture contains 32 echo cancellers divided into 16 groups. each group has two echo cancellers which can be individually controlled (echo canceller a (eca) and echo canceller b (ecb). they can be set in three distinct configurations: normal, back-to-back, and extended delay . see figures 6, 7, and 8. 2.1 normal configuration in normal configuration, the two echo cancellers (echo canceller a and b) are positioned in parallel, as shown in figure 6, providing 64 milliseconds of echo cancellation in two channels simultaneously.
zl50211 data sheet 15 zarlink semiconductor inc. figure 6 - normal device configuration (64 ms) 2.2 back-to-back configuration in back-to-back configuratio n, the two echo cancellers from the same group are positioned to cancel echo coming from both directions in a single channel providing fu ll-duplex 64ms echo cancel lation. see figure 7. this configuration uses only one timeslot on port1 and port 2 and the second timeslot nor mally associated with ecb contains zero code. back-to-back configuration allows a no-glue interface for applications where bidirectional echo cancellation is required. figure 7 - back-to-back device configuration (64 ms) back-to-back configuration is selected by writing a ?1? into the bbm bit of control register 1 for both echo canceller a and echo canceller b for a given group of echo canceller. table 4 shows the 16 groups of 2 cancellers that can be configured into back-to-back. examples of back-to-back configuration include positi oning one group of echo cancellers between a codec and a transmission device or between two codecs for echo control on analog trunks. rin rout sout sin echo path a echo path b + - channel a channel a + - channel b channel b eca ecb adaptive filter (64ms) adaptive filter (64ms) port1 port2 + eca sin sout rout rin - ecb + - echo echo path path adaptive filter (64ms) adaptive filter (64ms) port1 port2
zl50211 data sheet 16 zarlink semiconductor inc. 2.3 extended de lay configuration in this configuration, the two echo cancellers from the same group are internally cascaded into one 128 milliseconds echo canceller. see figure 8. this conf iguration uses only one time slot on port1 and port2 and the second timeslot normally associat ed with ecb contains quiet code. figure 8 - extended delay configuration (128 ms) extended delay configuration is selected by writing a ?1? into the extdl bit in echo canceller a, control register 1. for a given group, only echo canceller a, control regi ster 1, has the extdl bit. for echo canceller b control register 1, bit 0 must always be set to zero. table 4 shows the 16 groups of 2 cancellers that can each be configured into 64 ms or 128 ms echo tail capacity. 3.0 echo canceller functional states each echo canceller has four functional states: mute, bypass, disable adaptation and enable adaptation . 3.1 mute in normal and in extended delay confi gurations, writing a ?1? into the muter bit replaces rin with quiet code which is applied to both the adaptive filter and rout. writing a ?1? into the mutes bit replaces the sout pcm data with quiet code. in back-to-back configuration, writing a ?1? into the muter bit of echo canceller a, control register 2, causes quiet code to be transmitted on rout. writing a ?1? into the mutes bit of echo canceller a, control register 2, causes quiet code to be transmitted on sout. in extended delay and in back-to-back configurations, muter and mutes bits of echo canceller b must always be ?0?. refer to figure 4 and to control register 2 for bit description. linear 16 bits 2?s complement sign/ magnitude -law a-law ccitt (g.711) -law a-law +zero (quiet code) 0000 hex 80 hex ff hex d5 hex table 2 - quiet pcm code assignment + - channel a channel a eca sin sout rout rin echo path a adaptive filter (128 ms) port1 port2
zl50211 data sheet 17 zarlink semiconductor inc. 3.2 bypass the bypass state directly transfers pcm codes from rin to rout and from sin to sout. when bypass state is selected, the adaptive filter coefficients are reset to zero. bypass state must be selected for at least one frame (125 s) in order to properly clear the filter. 3.3 disable adaptation when the disable adaptation state is selected, the adaptive fi lter coefficients are frozen at their current value. the adaptation process is halted, however, the echo canceller continues to cancel echo. 3.4 enable adaptation in enable adaptation state, the adaptive filter coefficients are continually u pdated. this allows the echo canceller to model the echo return path characteristics in orde r to cancel echo. this is the normal operating state. the echo canceller functions are selected in control regi ster 1 and control register 2 through four control bits: mutes, muter, bypass and adaptdis. refer to the evp registers description for details. 4.0 echo voice processo r (evp) throughput delay the throughput delay of the evp varies according to the device configuration. for all device configurations, rin to rout has a delay of two frames and sin to sout has a delay of three frames. in bypass state, the rin to rout and sin to sout paths have a delay of two frames. 5.0 serial pcm i/o channels there are four tdm i/o streams, each wi th channels numbered from 0 to 31. one input stream is for receive (rin) channels, and the other input stream is for send (sin) c hannels. likewise, two output streams is for rout pcm channels, and sout pcm channels. s ee figure 9 for channel allocation. 5.1 serial data interface timing the zl50211 provides st-bus and gci interface timing. the serial interface clock frequency, c4i , is 4.096 mhz. the input and output data rate of the st-bus and gci bus is 2.048 mb/s. the 8 khz input frame pulse can be in either st-bus or gci format. the evp automatically detects the presence of an input frame pulse and identifies it as either st-bus or gci. in st-bus format, every second falling edge of the c4i clock marks a bit boundary, and the data is clocked in on the rising edge of c4i , three quarters of the way into the bit cell (see figure 11). in gci format, every second rising edge of the c4i clock marks the bit boundary, and data is clocked in on the second falling edge of c4i , half the way into the bit cell (see figure 12). figure 9 - st-bus and gci interface channel assignment for 2 mb/s data streams f0i rin/sin rout/sout channel 31 channel 0 125 sec channel 1 channel 30 st-bus f0i gci interface note: refer to figure 11 and figure 12 for timing details.
zl50211 data sheet 18 zarlink semiconductor inc. 6.0 memory mapped control and status registers internal memory and registers are memory mapped into the address space of the host interface. the internal dual ported memory is mapped into segments on a ?per channe l? basis to monitor and control each individual echo canceller and associated pcm channels. for example, in normal configuration , echo canceller #5 makes use of echo canceller b from group 2. it occupies the internal address space from 0a0 hex to 0bf hex and interfaces to pcm channel #5 on all serial pcm i/o streams. as illustrated in table 3, the ?per channel? registers pr ovide independent cont rol and status bits for each echo canceller. figure 10 shows the memory map of the control/status register blocks for all echo cancellers of the evp. when extended delay or back-to-back configuration is selected, control register 1 of eca and ecb and control register 2 of the selected group of echo cancellers requ ire special care. refer to t he evp register description section. base address + echo canceller a base address + echo canceller b ms byte ls byte ms byte ls byte -00 hex control reg 1 - 20 hex control reg 1 -01 hex control reg 2 - 21 hex control reg 2 -02 hex status reg - 22 hex status reg -03 hex reserved - 23 hex reserved -04 hex flat delay reg - 24 hex flat delay reg -05 hex reserved - 25 hex reserved -06 hex decay step size reg - 26 hex decay step size reg -07 hex decay step number - 27 hex decay step number -08 hex control reg 3 - 28 hex control reg 3 -09 hex control reg 4 - 29 hex control reg 4 -0a hex noise scaling - 2a hex noise scaling -0b hex noise control - 2b hex noise control 0d hex 0c hex rin peak detect reg 2d hex 2c hex rin peak detect reg 0f hex 0e hex sin peak detect reg 2f hex 2e hex sin peak detect reg 11 hex 10 hex error peak detect reg 31 hex 30 hex error peak detect reg 13 hex 12 hex reserved 33 hex 32 hex reserved 15 hex 14 hex dtdt reg 35 hex 34 hex dtdt reg 17 hex 16 hex reserved 37 hex 36 hex reserved 19 hex 18 hex nlpthr 39 hex 38 hex nlpthr 1b hex 1a hex step size, mu 3b hex 3a hex step size, mu 1d hex 1c hex gains 3d hex 3c hex gains 1f hex 1e hex reserved 3f hex 3e hex reserved table 3 - memory mapping of per channel control and status registers
zl50211 data sheet 19 zarlink semiconductor inc. table 4 is a list of the channels used for the 16 grou ps of echo cancellers when they are configured as extended delay or back-to-back. 7.0 normal configuration for a given group (group 0 to 15), 2 pcm i/o channels are used. for example, group 1 echo cancellers a and b, channels 2 and 3 are active. 7.1 extended de lay configuration for a given group (group 0 to 15), only one pcm i/o channel is active (echo canceller a) and the other channel carries quiet code. for example, group 2, echo canc eller a (channel 4) will be active and echo canceller b (channel 5) will carry quiet code. 7.2 back-to-back configuration for a given group (group 0 to 15), only one pcm i/o channel is active (echo canceller a) and the other channel carries quiet code. for example, group 5, echo cancelle r a (channel 10) will be active and echo canceller b (channel 11) will carry quiet code. group channels group channels 00, 1816, 17 12, 3918, 19 2 4, 5 10 20, 21 3 6, 7 11 22, 23 4 8, 9 12 24, 25 5 10, 11 13 26, 27 6 12, 13 14 28, 29 7 14, 15 15 30, 31 table 4 - group and channel allocation
zl50211 data sheet 20 zarlink semiconductor inc. figure 10 - memory mapping 7.3 power up sequence on power up, the reset pin must be held low for 100 s. forcing the reset pin low will put each evp in power down state. in this state, all internal clocks are hal ted, d<7:0>, sout, rout, dta and irq pins are tristated. the 16 main control registers, the inte rrupt fifo register and the test register are reset to zero. when the reset pin returns to logic high and a valid mclk is applied, the user must wait 500 s for the pll to lock. c4i and f0i can be active during this period. once the pll has locked, the user must power up the 16 groups of echo cancellers individually, by writing a ?1? into the pwup bit in each group of echo canceller?s main control register. for each group of echo cancellers, when the pwup bit toggles from zero to one, echo cancellers a and b execute their initialization routin e. the initialization routine sets their registers, base address+00 hex to base address+3f hex , to the default power-up value and clears the adaptive filter coefficients. two frames are necessary for the initialization routine to execute properly. once the initialization routine is executed, the user c an set the per channel control registers, base address+00 hex to base address+3f hex , for the specific application. 7.4 power management each group of echo cancellers can be placed in power down mode by writing a ?0? into the pwup bit in their respective main control register. when a given group is in power down mode, the corresponding pcm data are bypassed from rin to rout and from sin to sout with two frames delay. refer to the main control register section for description. the typical power consumption can be ca lculated with the following equation: p c = 9 * nb_of_groups + 3.6, in mw where 0 nb_of_groups 16. 0000h --> channel 0, eca ctrl/stat registers 001fh 0020h --> channel 1, ecb ctrl/stat registers 003fh 0040h --> channel 2, eca ctrl/stat registers 005fh 0060h --> channel 3, ecb ctrl/stat registers 007fh 03c0h --> channel 30, eca ctrl/stat registers 03dfh 03e0h --> channel 31, ecb ctrl/stat registers 03ffh 0400h --> 040fh main control registers <15:0> group 0 echo cancellers registers groups 2 --> 14 echo cancellers registers group 1 echo cancellers registers group 15 echo cancellers registers 0410h interrupt fifo register 0411h test register 0412h ---> ffffh reserved test register
zl50211 data sheet 21 zarlink semiconductor inc. 7.5 call initialization to ensure fast initial convergence on a new call, it is important to clear the adaptive filter. this is done by putting the echo canceller in bypass mode for at least one frame (125 s) and then enabling adaptation. since the narrow band detector is ?on? regardless of the functional state of the echo canceller it is recommended that the echo cancellers are reset bef ore any call progress tones are applied. 7.6 interrupts the evp provides an interrupt pin (irq ) to indicate to the host processor when a g.164 or g.165 tone disable is detected and released. although each evp may be configured to react automatically to tone dis able status on any input pcm voice channels, the user may want for the ex ternal host processor to respond to tone disable information in an appropriate application-specific manner. each echo canceller will generate an interrupt when a tone disable occurs and w ill generate another interrupt when a tone disable releases. upon receiving an irq , the host cpu should read the interrupt fifo register. this register is a fifo memory containing the channel number of the echo canceller that has generated the interrupt. all pending interrupts from any of the echo cancellers and their associated input chan nel number are stored in this fifo memory. the irq always returns high after a read access to the interrupt fifo register. the irq pin will toggle low for each pending interrupt. after the host cpu has received the channel number of the interrupt source, the corresponding per channel status register can be read from inte rnal memory to determine the cause of the interrupt (see table 3 for address mapping of status register). the td bit indicates the presence of a tone disable. the mirq bit 5 in the main control register 0 masks interrup ts from the evp. to provide more flexibility, the mtdbi (bit-4) and mtdai (bit-3) bits in the main control re gister<15:0> allow tone disable to be masked or unmasked from generating an interrupt on a per channel bas is. refer to the registers description section. 8.0 jtag support the evp jtag interface conforms to the boundary-scan standard ieee1149.1 . this standard specifies a design- for-testability technique called boundary-scan test (bst). the operation of the boundary scan circuitry is controlled by an test access port (tap) controller. jtag inputs are 3.3 volts compliant only. 8.1 test access port (tap) the tap provides access to many test functions of the evp. it consists of four inpu t pins and one output pin. the following pins are found on the tap. ? test clock input (tck) the tck provides the clock for the test logic. the tc k does not interfere with any on-chip clock and thus remains independent. the tck permits shifting of test dat a into or out of the boundary-scan register cells concurrent with the operation of the device and without interfering wi th the on-chip logic. ? test mode select input (tms) the logic signals received at the tms input are interp reted by the tap controller to control the test operations. the tms signals are sampled at the rising edge of the tck pulse. this pin is internally pulled to v dd1 when it is not driven from an external source. ? test data input (tdi) serial input data applied to this port is fed either into the instruction re gister or into a test data register, depending on the sequence previously applied to the tms input. both registers are described in a
zl50211 data sheet 22 zarlink semiconductor inc. subsequent section. the received input data is samp led at the rising edge of tck pulses. this pin is internally pulled to v dd1 when it is not driven from an external source. ? test data output (tdo) depending on the sequence previously applied to the tm s input, the contents of either the instruction register or data register are serially shifted out to wards the tdo. the data from the tdo is clocked on the falling edge of the tck pulses. when no data is shifte d through the boundary scan cells, the tdo driver is set to a high impedance state. ? test reset (trst ) this pin is used to reset the jtag scan structure. this pin is internally pulled to v ss . 8.2 instruction register in accordance with the ieee 1149.1 standar d, the evp uses public instructions. the jtag interface contains a 3-bit instruction register. instructions are serially loaded in to the instruction register from the tdi when the tap controller is in its shifted-ir state. subsequently, the in structions are decoded to achieve two basic functions: to select the test data register that will operate while the instruction is current, a nd to define the serial test data register path, which is used to shift data between tdi and tdo during data register scanning. 8.3 test data registers as specified in ieee 11 49.1, each of the echo voice processor?s jtag interface contains three test data registers: ? boundary-scan register the boundary-scan register consists of a series of boundary-scan cells arranged to form a scan path around the boundary of each evp core logic. ? bypass register the bypass register is a single stage shift register that provides a one-bit path from tdi to tdo. ? device identification register the device identification register provides access to the following encoded information: device version number, part number and manufacturer's name.
zl50211 data sheet 23 zarlink semiconductor inc. * exceeding these values may cause permanent damage. functional operation under these conditions is not implied. . ? typical figures are at 25 c and are for design aid only: not guaranteed and not subject to production testing ? characteristics are over recommended operating conditions unless otherwise stated ? typical figures are at 25 c, v dd1 =3.3 v and are for design aid only: not guaranteed and not subject to production testing. absolute maximum ratings* parameter symbol min. max. units 1 i/o supply voltage (v dd1 )v dd_io -0.5 5.0 v 2 core supply voltage (v dd2 )v dd_core -0.5 2.5 v 3 input voltage v i3 v ss - 0.5 v dd1 +0.5 v 4 input voltage on any 5 v tolerant i/o pins v i5 v ss - 0.3 7.0 v 5 continuous current at digital outputs i o 20 ma 6 package power dissipation p d 3.0 w 7 storage temperature t s -55 150 c recommended operating conditions - voltages are with respect to ground (vss) unless otherwise stated characteristics sym. min. typ. ? max. units 1 operating temperature t op -40 +85 c 2 i/o supply voltage (v dd_io )v dd1 3.0 3.3 3.6 v 3 core supply voltage (v dd_core )v dd2 1.6 1.8 2.0 v 4 input high voltage on 3.3 v tolerant i/o v ih3 0.7v dd1 v dd1 v 5 input high voltage on 5 v tolerant i/o pins v ih5 0.7v dd1 5.5 v 6 input low voltage v il 0.3v dd1 v dc electrical characteristics ? - voltages are with respect to ground (v ss ) unless otherwise stated. characteristics sym. min. typ. ? max. units test conditions 1 i n p u t s static supply current i cc 250 a reset = 0 idd_io (v dd1 = 3.3 v) single ev processor i dd_io 10 ma 32 channels of single evp are active idd_core (v dd2 = 1.8 v) single ev processor i dd_core 65 ma 32 channels of single evp are active 2 power consumption p c 1.2 w all evp?s i.e., 256 chan- nels are active 3 input high voltage v ih 0.7v dd1 v 4 input low voltage v il 0.3v dd1 v 5 input leakage input leakage on pullup input leakage on pulldown i ih /i il i lu i ld 10 -100 100 a a a v in =v ss to v dd1 or 5.5 v v in =v ss v in =v dd1 6 input pin capacitance c i 10 pf 7 o u t p u t s output high voltage v oh 0.8v dd1 vi oh = 12 ma 8 output low voltage v ol 0.4 v i ol = 12 ma 9 high impedance leakage i oz 10 av in =v ss to 5.5 v 10 output pin capacitance c o 10 pf
zl50211 data sheet 24 zarlink semiconductor inc. ? characteristics are over recommended operating conditions unless otherwise stated ? characteristics are over recommended operating conditions unless otherwise stated ? typical figures are at 25 c, v dd1 = 3.3 v and for design aid only: not guaranteed and not subject to production testing ? characteristics are over recommended operating conditions unless otherwise stated ? typical figures are at 25 c, v dd1 = 3.3 v and for design aid only: not guaranteed and not subject to production testing ? characteristics are over recommended operating conditions unless otherwise stated ? typical figures are at 25 c, v dd1 = 3.3 v and for design aid only: not guaranteed and not subject to production testing ac electrical characteristics ? - timing parameter measurement voltage levels - voltages are with respect to ground (v ss ) unless otherwise stated. characteristics sym. level units conditions 1 cmos threshold v tt 0.5v dd1 v 2 cmos rise/fall threshold voltage high v hm 0.7v dd1 v 3 cmos rise/fall threshold voltage low v lm 0.3v dd1 v ac electrical characteristics ? - frame pulse and c4i characteristic sym. min. typ. ? max. units notes 1 frame pulse width (st-bus, gci) t fpw 20 2* t cp -20 ns 2 frame pulse setup time before c4i falling (st-bus or gci) t fps 10 122 150 ns 3 frame pulse hold time from c4i falling (st-bus or gci) t fph 10 122 150 ns 4 c4i period t cp 190 244 300 ns 5 c4i pulse width high t ch 85 150 ns 6 c4i pulse width low t cl 85 150 ns 7 c4i rise/fall time t r , t f 10 ns ac electrical characteristics ? - serial streams for st-bus and gci backplanes characteristic sym. min. typ. ? max. units test conditions 1 rin/sin set-up time t sis 10 ns 2 rin/sin hold time t sih 10 ns 3 rout/sout delay - active to active t sod 60 ns 4 output data enable (ode) delay t ode 30 ns ac electrical characteristics ? - master clock - voltages are with respect to ground (v ss ). unless otherwise stated. characteristic sym. min. typ. ? max. units notes 1 master clock frequency, - fsel = 0 - fsel = 1 f mcf0 f mcf1 19.0 9.5 20.0 10.0 21.0 10.5 mhz mhz 2 master clock low t mcl 20 ns 3 master clock high t mch 20 ns
zl50211 data sheet 25 zarlink semiconductor inc. ? characteristics are over recommended operating conditions unless otherwise stated ? typical figures are at 25 c, v dd1 = 3.3 v and for design aid only: not guaranteed and not subject to production testing figure 11 - st-bus timing at 2.048 mb/s ac electrical ch aracteristics ? - motorola non-multiplexed bus mode characteristics sym. min. typ. ? max. units test conditions 1cs setup from ds falling t css 0ns 2r/w setup from ds falling t rws 0ns 3 address setup from ds falling t ads 0ns 4cs hold after ds rising t csh 0ns 5r/w hold after ds rising t rwh 0ns 6 address hold after ds rising t adh 0ns 7 data delay on read t ddr 79 ns 8 data hold on read t dhr 315ns 9 data setup on write t dsw 0ns 10 data hold on write t dhw 0ns 11 acknowledgment delay t akd 80 ns 12 acknowledgment hold time t akh 08ns 13 irq delay t ird 20 65 ns v tt v tt f0i c4i t fpw rout/sout rin/sin t fph t sod t sih t ch t cl bit 0, channel 31 t fps t cp t sis v tt v tt bit 7, channel 0 bit 6, channel 0 bit 5, channel 0 bit 0, channel 31 bit 7, channel 0 bit 6, channel 0 bit 5, channel 0 v hm v lm t r t f
zl50211 data sheet 26 zarlink semiconductor inc. figure 12 - gci interface timing at 2.048 mb/s figure 13 - output driver enable (ode) figure 14 - master clock v tt v tt f0i c4i t fpw sout/rout sin/rin t fph t sod t sih t ch t cl bit 7, channel 31 t fps t cp t sis v tt v tt bit 0, channel 0 bit 1, channel 0 bit 2, channel 0 bit 7, channel 31 bit 0, channel 0 bit 1, channel 0 bit 2, channel 0 t r t f v hm v lm v tt hiz hiz sout/rout ode t ode t ode valid data v tt t mch t mcl v tt mclk
zl50211 data sheet 27 zarlink semiconductor inc. figure 15 - motorola non-multiplexed bus timing ds a0-a12 cs d0-d7 d0-d7 read write t css t csh t adh t dhr t rws r/w t ads t rwh t dhw t akd t dsw t ddr t akh dta v tt v tt v tt v tt v tt v tt v tt valid address valid read data valid write data t ird irq v tt
zl50211 data sheet 28 zarlink semiconductor inc. 9.0 evp registers description echo canceller a (eca): control register 1 power-up 00 hex r/w address: 00 hex + base address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset injdis bbm pad bypass adpdis 0 extdi functional descripti on of register bits reset when high, the power-up initialization is exec uted. this presets all r egister bits including this bit and clears the adaptive filter coefficients. injdis when high, the noise injection process is di sabled. when low noise injection is enabled. bbm when high, the back to back configuration is enabled. when low, the normal configuration is enabled. note: do not enabl e extended-delay and bbm configurations at the same time. always set both bbm bits of the two echo cancellers (control register 1) of the same group to the same logic value to avoid conflict. pad when high, 12 db of attenuation is inserted in to the rin to rout path. when low, the gains register controls the signal levels. bypass when high, sin data is by-passed to sout and rin data is by-passed to rout. the adaptive filter coefficients are set to zero and the filter adaptation is stopped. when low, output data on both sout and rout is a func tion of the echo canceller algorithm. adpdis when high, echo canceller adaptation is disabled. the voice processor cancels echo. when low, the echo canceller dynamically adapts to the echo path characteristics. 0 bits marked as ?1? or ?0? are reserved bits and should be written as indicated. extdl when high, echo cancellers a and b of the same group are internally cascaded into one 128 ms echo canceller. when low, echo cancellers a and b of the same group operate independently. echo canceller b (ecb): control register 1 power-up 02 hex r/w address: 20 hex + base address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset injdis bbm pad bypass adpdis 1 0 functional descripti on of register bits reset when high, the power-up initialization is exec uted which presets all r egister bits including this bit and clears the adaptive filter coefficients. injdis when high, the noise injection process is di sabled. when low, noise injection is enabled. bbm when high, the back to back configuration is enabled. when low, the normal configuration is enabled. note: do not enabl e extended-delay and bbm configurations at the same time. always set both bbm bits of the two echo cancellers (control register 1) of the same group to the same logic value to avoid conflict. pad when high, 12 db of attenuation is inserted in to the rin to rout path. when low, the gains register controls the signal levels. bypass when high, sin data is by-passed to sout and rin data is by-passed to rout. the adaptive filter coefficients are set to zero and the filter adaptation is stopped. when low, output data on both sout and rout is a func tion of the echo canceller algorithm. adpdis when high, echo canceller adaptation is disabled. the voice processor cancels echo. when low, the echo canceller dynamically adapts to the echo path characteristics. 1 bits marked as ?1? or ?0? are reserved bits and should be written as indicated. 0 control register 1 (echo canceller b) bit 0 is a reserved bit and should be written ?0?.
zl50211 data sheet 29 zarlink semiconductor inc. note: in order to correctly write to control register 1 and 2 of ecb, it is necessary to write the data twice to the register, o ne immediately after another. the two writes must be separated by at least 350 ns and no more than 20 us. power-up 00 hex eca: control register 2 r/w address: 01 hex + base address ecb: control register 2 r/w address: 21 hex + base address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tdis phdis nlpdis autotd nbdis hpfdis mutes muter functional descripti on of register bits tdis when high, tone detection is disabled. when lo w, tone detection is enabled. when both echo cancellers a and b tdis bits are high, tone disa ble processors are disa bled entirely and are put into power down mode. phdis when high, the tone detectors will trigger upon th e presence of a 2100 hz tone regardless of the presence/absence of peri odic phase reversals. when low, th e tone detectors w ill trigger only upon the presence of a 2100 hz tone with periodic phase reversals. nlpdis when high, the non-linear processo r is disabled. when low, the no n-linear processors function normally. useful for g.165 conformance testing. autotd when high, the echo canceller puts itself in bypass mode when the tone detectors detect the presence of 2100 hz tone. see phdi s for qualification of 2100 hz tones. when low, the echo canceller algorithm will remain operational regardless of the state of the 2100 hz tone detectors. nbdis when high, the narrow-band detector is di sabled. when low, the narrow-band detector is enabled. hpfdis when high, the offset nulling high pass filter s are bypassed in the rin and sin paths. when low, the offset nulling filters are active and w ill remove dc offsets on pcm input signals. mutes when high, data on sout is muted to quiet code. when low, sout carries active code. muter when high, data on rout is muted to quiet code. when low, rout carries active code.
zl50211 data sheet 30 zarlink semiconductor inc. power-up 00 hex eca: status register r/w address: 02 hex + base address ecb: status register r/w address: 22 hex + base address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserve td dtdet reserve reserve reserve tdg nb functional descripti on of register bits reserve reserved bit. td logic high indicates the pr esence of a 2100 hz tone. dtdet logic high indicates the presence of a double-talk condition. reserve reserved bit. reserve reserved bit. reserve reserved bit. tdg tone detection status bit gated with t he autotd bit. (control register 2). logic high indicates that autotd has been enab led and the tone detector has detected the presence of a 2100 hz tone. nb logic high indicates the presence of a narrow-band signal on rin. power-up 00 hex eca: flat delay register (fd) r/w address: 04 hex + base address ecb: flat delay register (fd) r/w address: 24 hex + base address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 fd7 fd6 fd5 fd4 fd3 fd2 fd1 fd0 power-up 00 hex eca: decay step number register (ns) r/w address: 07 hex + base address ecb: decay step number register (ns) r/w address: 27 hex + base address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ns7 ns6 ns5 ns4 ns3 ns2 ns1 ns0 power-up 00 hex eca: decay step size control register (ssc) r/w address: 06 hex + base address ecb: decay step size control register (ssc) r/w address: 26 hex + base address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 0 0 0 0 ssc2 ssc1 ssc0 note: bits marked with ?0? are reserved bits and should be written ?0?
zl50211 data sheet 31 zarlink semiconductor inc. figure 16 - the mu profile functional description of register bits the exponential decay registers (decay step number and decay step size) and flat delay register allow the lms adaptation step-size (mu) to be programm ed over the length of the fir filter. a programmable mu profile allows the performance of the echo canceller to be optimized for specific applications. for example, if the characteristic of the echo response is known to hav e a flat delay of several milliseconds and a roughly exponential decay of the echo impulse response, then the mu profile can be programmed to approximate this expected impulse response thereby improving the convergence characteristics of the adaptive filter. note that in the following register descriptions, one tap is equivalent to 125 s (64 ms/512 taps). fd 7-0 flat delay : this register defines the flat delay of the mu profile, (i.e., where the mu value is 2 -16 ). the delay is defined as fd 7-0 x 8 taps. for example; if fd 7-0 = 5, then mu=2 -16 for the first 40 taps of the echo canceller fir filter. the valid range of fd 7-0 is: 0 fd 7-0 64 in normal mode and 0 fd 7-0 128 in extended-delay mode. the default value of fd 7-0 is zero. ssc 2-0 decay step size control : this register controls the step size (ss) to be used during the exponential decay of mu. the decay rate is defined as a decrease of mu by a factor of 2 every ss taps of the fir filter, where ss = 4 x2 ssc 2-0 . for example; if ssc 2-0 = 4, then mu is reduced by a factor of 2 every 64 taps of the fir filter. the default value of ssc 2-0 is 04 hex . ns 7-0 decay step number : this register defines the number of steps to be used for the decay of mu where each step has a period of ss taps (see ssc 2-0 ). the start of the exponential decay is defined as: filter length (512 or 1024) - [decay step number (ns 7-0 ) x step size (ss)] where ss = 4 x2 ssc 2-0 . for example; if ns 7-0 =4 and ssc 2-0 =4, then the exponential decay start value is 512 - [ns 7-0 x ss] = 512 - [4 x (4x2 4 )] = 256 taps for a filter length of 512 taps. amplitude of mu time flat delay (fd 7-0 ) step size (ss) 1.0 2 -16 fir filter length (512 or 1024 taps) number of steps (ns 7-0 )
zl50211 data sheet 32 zarlink semiconductor inc. table 5 below is the same table shown on page 9. power-up fb hex eca: control register 3 r/w address: 08 hex + base address ecb: control register 3 r/w address: 28 hex + base address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 nlrun2 injctrl nlrun1 ringclr reserve pathclr pathdet nlpsel functional descripti on of register bits nlrun2 when high, the comfort noise level estimato r actively rejects double-talk as being background noise. when low, the noise level es timator makes no such distinction. injctrl selects which noise ramping scheme is used. see table below. nlrun1 when high, the comfort noise level estimato r actively rejects uncancelled echo as being background noise. when low, the noise level estimator makes no such distinction. ringclr when high, the instability detector is activated. when low, the instability detector is disabled. reserve reserved bit. must always be set to one for normal operation. pathclr when high, the curr ent echo channel estimate will be clear ed and the echo canc eller will enter fast convergence mode u pon detection of a path change. when low, the echo canceller will keep the current path estimate but revert to fast convergence mode upon detection of a path change. note: this bit is ignored if pathdet is low. pathdet when high, the path change detector is activated. when low, the path change detector is disabled. nlpsel when high, the advanced nlp is selected. when low, the original nlp is selected. feature register or bit(s) advanced nlp default value original nlp default value nlp selection nlpsel (control register 3) 1 0 (feature not supported) reject uncancelled echo as noise nlrun1 (control regist er 3) 1 0 (feature not supported) reject double-talk as noise nlrun2 (control register 3) 1 0 (feature not supported) noise level estimator ramping scheme injctrl (control register 3) 1 0 (feature not supported) noise level ramping rate nlinc (noise control) 5 hex c hex noise level scaling noise scaling 16 hex 74 hex table 5 - comparison of the nlp types
zl50211 data sheet 33 zarlink semiconductor inc. power-up 54 hex eca: control register 4 r/w address: 09 hex + base address ecb: control register 4 r/w address: 29 hex + base address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 sd2 sd1 sd0 0 slow2 slow1 slow0 functional descripti on of register bits 0 must be set to zero. supdec these three bits (sd2,sd1,sd0) control how long the echo canceller remains in a fast convergence state following a path change, reset or bypass operation. a value of zero will keep the echo canceller in fast convergence indefinitely. 0 must be set to zero. slow slow convergence mode speed adju stment.(bits slow2, slow1,slow0) for slow = 1, 2,..., 7, slow convergence speed is reduced by a factor of 2 slow as compared to normal adaptation. for slow = 0, no adaptation occurs during slow convergence. power-up 16 hex eca: noise scaling (ns) r/w address: 0a hex + base address ecb: noise scaling (ns) r/w address: 2a hex + base address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ns7 ns6 ns5 ns4 ns3 ns2 ns1 ns0 functional descripti on of register bits this register is used to scale the co mfort noise up or down. larger values will increase the relative level of comfort noise. the default value of 16 hex will provide g.168 compliance with the advanced nlp. a value of 74 hex is recommended if the original nlp is used. power-up 45 hex eca: noise control r/w address: 0b hex + base address ecb: noise control r/w address: 2b hex + base address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserve reserve reserve reserve nlinc3 nlinc2 nlinc1 nlinc0 functional descripti on of register bits reserve reserved bits. must be set to 4 hex for normal operation. nlinc noise level estimator ramping rate. when injctrl = 1, a lower value will give faster ramping. when injctrl = 0, a higher value will give faster ramping. the default value of 5 hex will provide g.168 compliance with injctrl = 1. a value of c hex is recommended if injctrl = 0.
zl50211 data sheet 34 zarlink semiconductor inc. power-up n/a eca: rin peak detect register 2 (rp) r/w address: 0d hex + base address ecb: rin peak detect register 2 (rp) r/w address: 2d hex + base address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rp15 rp14 rp13 rp12 rp11 rp10 rp9 rp8 power-up n/a eca: rin peak detect register 1 (rp) r/w address: 0c hex + base address ecb: rin peak detect register 1 (rp) r/w address: 2c hex + base address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rp7 rp6 rp5 rp4 rp3 rp2 rp1 rp0 functional descripti on of register bits these peak detector registers allow the user to monitor the receive in (rin) peak si gnal level. the information is in 16-bit 2?s complement linear coded format pres ented in two 8 bit registers fo r each echo canceller. the high byte is in register 2 and the low byte is in register 1. power-up n/a eca: sin peak detect register 2 (sp) r/w address: 0f hex + base address ecb: sin peak detect register 2 (sp) r/w address: 2f hex + base address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sp15 sp14 sp13 sp12 sp11 sp10 sp9 sp8 power-up n/a eca: sin peak detect register 1 (sp) r/w address: 0e hex + base address ecb: sin peak detect register 1 (sp) r/w address: 2e hex + base address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0 functional descripti on of register bits these peak detector registers allow the us er to monitor the send in (sin) peak signal level. the information is in 16-bit 2?s complement linear coded format presented in two 8 bit registers for each echo canceller. the high byte is in register 2 and the low byte is in register 1.
zl50211 data sheet 35 zarlink semiconductor inc. power-up n/a eca: error peak detect register 2 (ep) r/w address: 11 hex + base address ecb: error peak detect register 2 (ep) r/w address: 31 hex + base address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ep15 ep14 ep13 ep12 ep11 ep10 ep9 ep8 power-up n/a eca: error peak detect register 1 (ep) r/w address: 10 hex + base address ecb: error peak detect register 1 (ep) r/w address: 30 hex + base address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ep7 ep6 ep5 ep4 ep3 ep2 ep1 ep0 functional descripti on of register bits these peak detector registers allow the user to monitor the error signal peak level. t he information is in 16-bit 2?s complement linear coded format presented in two 8 bit registers for each echo canceller. the high byte is in register 2 and the low byte is in register 1. power-up 48 hex eca: double-talk detection threshold register 2 r/w address: 15 hex + base address ecb: double-talk detection threshold register 2 r/w address: 35 hex + base address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 dtdt15 dtdt14 dtdt13 dtdt12 dtdt11 dtdt10 dtdt9 dtdt8 power-up 00 hex eca: double-talk detection threshold register 1 r/w address: 14 hex + base address ecb: double-talk detection threshold register 1 r/w address: 34 hex + base address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 dtdt7 dtdt6 dtdt5 dtdt4 dtdt3 dtdt2 dtdt1 dtdt0 functional descripti on of register bits this register allows the user to program the level of double-talk detection threshold (dtdt). the 16 bit 2?s complement linear value defaults to 4800 hex = 0.5625 or -5 db. the maximum value is 7fff hex = 0.9999 or 0 db. the high byte is in register 2 and the low byte is in register 1.
zl50211 data sheet 36 zarlink semiconductor inc. power-up 0c hex eca: non-linear proces sor threshold register 2 (nlpthr) r/w address: 19 hex + base address ecb: non-linear proces sor threshold register 2 (nlpthr) r/w address: 39 hex + base address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 nlp15 nlp14 nlp13 nlp12 nlp11 nlp10 nlp9 nlp8 power-up e0 hex eca: non-linear proces sor threshold register 1 (nlpthr) r/w address: 18 hex + base address ecb: non-linear proces sor threshold register 1 (nlpthr) r/w address: 38 hex + base address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 nlp7 nlp6 nlp5 nlp4 nlp3 nlp2 nlp1 nlp0 functional descripti on of register bits this register allows the user to pr ogram the level of the non-linear proc essor threshold (nlpthr). the 16 bit 2?s complement linear value defaults to 0ce0 hex = 0.1 or -20.0 db. the maximum value is 7fff hex = 0.9999 or 0 db. the high byte is in register 2 and the low byte is in register 1. power-up 40 hex eca: adaptation step size register 2 (mu) r/w address: 1b hex + base address ecb: adaptation step size register 2 (mu) r/w address: 3b hex + base address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 mu15 mu14 mu13 mu12 mu11 mu10 mu9 mu8 power-up 00 hex eca: adaptation step size register 1 (mu) r/w address: 1a hex + base address ecb: adaptation step size register 1 (mu) r/w address: 3a hex + base address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 mu7 mu6 mu5 mu4 mu3 mu2 mu1 mu0 functional descripti on of register bits this register allows the user to program the level of mu . mu is a 16 bit 2?s complement value which defaults to 4000 hex = 1.0 the maximum value is 7fff hex or 1.9999 decimal. the high byte is in register 2 and the low byte is in register 1.
zl50211 data sheet 37 zarlink semiconductor inc. power-up 44 hex eca: gains register 2 r/w address: 1d hex + base address ecb: gains register 2 r/w address: 3d hex + base address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 rin2 rin1 rin0 0 rout2 rout1 rout0 power-up 44 hex eca: gains register 1 r/w address: 1c hex + base address ecb: gains register 1 r/w address: 3c hex + base address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 sin2 sin1 sin0 0 sout2 sout1 sout0 functional descripti on of register bits this register is used to select gain values on ri n, rout, sin and sout. gains has the following structure: rin rout sin sout gains = 0xxx 0xxx 0xxx 0xxx = 0100 0100 0100 0100 (4444 hex ) default gains is split into four groups of four bits. each group maps to a different signal port (as indicated above), and has three gain bits. the following table indicates how these gain bits are used: bit2 bit1 bit0 gain level 1 0 0 0 db (default) 0 1 1 -3 db 0 1 0 -6 db 0 0 1 -9 db 0 0 0 -12 db note that the -12 db pad bit in cont rol register 1 provides 12 db of atte nuation in the rin to rout path, and will override the settings in gains.
zl50211 data sheet 38 zarlink semiconductor inc. main control register 0 (ec group 0) power-up 00 hex r/w address: 400 hex bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 wr_all ode mirq mtdbi mtdai format law pwup functional descripti on of register bits wr_all write all control bit: when high, group 0-15 echo cancelle rs registers are mapped into 0000 hex to 0003f hex which is group 0 address mapping. useful to initialize the 16 groups of echo cancellers as per group 0. when low, address mapping is per figure 10. note: only the main control register 0 has the wr_all bit ode output data enable: this control bit is logically and?d with the ode input pin. when both ode bit and ode input pin are high, the rout and sout out puts are enabled. when the ode bit is low or the ode input pin is low, the r out and sout outputs are high impedance . note: only the main control register 0 has the ode bit. mirq mask interrupt: when high, all the interrupts fr om the tone detectors output are masked. the tone detectors operate as specified in thei r echo canceller b, control register 2. when low, the tone detectors interrupts are active. note: only the main control register 0 has the mirq bit. mtdbi mask tone detector b interrupt: when high, the tone detector interrupt output from echo canceller b is masked. the tone detector operates as specified in echo canceller b, control register 2. when low, the tone detector b interrupt is active. mtdai mask tone detector a interrupt: when high, the tone detector interrupt output from echo canceller a is masked. the tone detector operates as specified in echo canceller a, control register 2. when low, the tone detector a interrupt is active. format itu-t/sign mag: when high, both echo cancel lers a and b for a given group, accept itu-t (g.711) pcm code. when low, both echo cancellers a and b for a given group, accept sign- magnitude pcm code. law a/ law: when high, both echo cancellers a and b for a given group, accept a-law companded pcm code. when low, both echo cancellers a and b for a given group, accept -law companded pcm code. pwup power-up: when high, both echo cancellers a and b and tone detectors for a given group, are active. when low, both echo cancellers a and b and tone detectors for a given group, are placed in power down mode. in this mode, the corresponding pcm data are bypassed from rin to rout and from sin to sout with two frames delay. when the pwup bit toggles from zero to one, the echo canceller a and b execute their initializati on routine which presets their registers, base address+00 hex to base address+3f hex , to the default power up va lue and clears the adaptive filter coefficients. two frames are necessary for th e initialization routine to execute properly. once the initialization routine is executed, the user can set the per channel control registers for their specific application.
zl50211 data sheet 39 zarlink semiconductor inc. main control register 1 (ec group 1) r/w address: 401 hex main control register 2 (ec group 2) r/w address: 402 hex main control register 3 (ec group 3) r/w address: 403 hex main control register 4 (ec group 4) r/w address: 404 hex main control register 5 (ec group 5) r/w address: 405 hex main control register 6 (ec group 6) r/w address: 406 hex main control register 7 (ec group 7) r/w address: 407 hex main control register 8 (ec group 8) r/w address: 408 hex main control register 9 (ec group 9) r/w address: 409 hex main control register 10 (ec group 10) r/w address: 40a hex main control register 11 (e c group 11) r/w address: 40b hex main control register 12 (ec group 12) r/w address: 40c hex main control register 13 (ec group 13) r/w address: 40d hex main control register 14 (ec group 14) r/w address: 40e hex main control register 15 (e c group 15) r/w address: 40f hex power-up 00 hex bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 unused unused unused mtdbi mtdai format law pwup functional descripti on of register bits unused unused bits. mtdbi mask tone detector b interrupt: when high, the tone detector interrupt ou tput from echo canceller b is masked. the tone detector operates as specified in echo canceller b, control register 2. when low, the tone detector b interrupt is active. mtdai mask tone detector a interrupt: when high, the tone detector interrupt ou tput from echo canceller a is masked. the tone detector operates as specified in echo canceller a, control register 2. when low, the tone detector a interrupt is active. format itu-t/sign mag: when high, bo th echo cancellers a and b for a given group, select itu-t (g.711) pcm code. when low, both echo cancellers a and b for a given group, select sign-magnitude pcm code . law a/ law: when high, both echo cancellers a and b for a given group, select a-law companded pcm code. when low, both echo cancellers a and b for a given group, select -law companded pcm code . pwup power-up: when high, both echo cancellers a and b and tone detectors for a given group, are active. when low, both echo cancellers a and b and tone detectors for a given group, are placed in power down mode. in this mode, the corresponding pcm data are bypassed from rin to rout and from sin to sout with two frames delay. when the pwup bit toggles from zero to one, the echo cancellers a and b execute their initializati on routine which presets their registers, base address+00 hex to base address+3f hex , to the default reset value and clears the adaptive filter coefficients. two frames are necessary for the in itialization routine to execute properly. once the initialization routine is executed, the user can set the per channel c ontrol registers fo r their specific application.
zl50211 data sheet 40 zarlink semiconductor inc. interrupt fifo register power-up 00 hex r/w address: 410 hex bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 irq0 0 i4i3i2i1i0 functional descripti on of register bits irq logic high indicates an interrupt has occurred. irq bit is cleared after the interrupt fifo register is read. logic low indicates that no interrupt is pending and the fifo is empty. 0 unused bit. always zero. 0 unused bit. always zero. i<4:0> i<4:0> binary code indicates the channel number at whic h a tone detector state change has occurred. note: whenever a tone disable is detected or released, an interrupt is generated. test register power-up 00 hex r/w address: 411 hex bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserve reserve reserve reserve reserve reserve reserve tirq functional description of register bits reserve reserved bits. must always be set to zero for normal operation. tirq test irq: useful for the appl ication engineer to verify the inte rrupt service routine. when high, any change to mtdbi and mt dai bits of the main control register will c ause an interrupt and its corresponding channel number will be available fr om the interrupt fifo register. when low, normal operation is selected.

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